MICROCOMPUTER WITH DISCONNECTED, OPEN, INDEPENDENT, BIMEMORY ARCHITECTURE, ALLOWING LARGE INTERACTING, INTERCONNECTED MULTI-MICROCOMPUTER PARALLEL SYSTEMS ACCOMMODATING MULTIPLE LEVELS OF PROGRAMMER DEFINED HIERARCHY
The meaning of the new mnemonics used in this specification are as follows:
BICPU - Bimemory Independent Central Processing Unit - This is the mnemonic for the invention. It comprises the basic CPU being implemented on the invention, plus the seven new switch means, the nine additional new registers, the two new ILUs, the new BIC-CTRB control lines, the new Interconnect Switch and the new "B" and "C" bus circuits.
BIM mode - BIMemory mode - This is one of eight different logical bimemory modes a BICPU can assume. In these eight BIM modes, a first BICPU microcomputer is in a logical bimemory hookup, controlling part or all of two standard memory circuits in a bimemory manner.
FLT mode - Floating mode - This is one of four different logical bimemory modes a "consenting" BICPU microcomputer can assume. In these four FLT modes, a "consenting" BICPU microcomputer has logically connected some or all of its "A" bus circuits and the standard memory circuits connected thereto, to the BICPU microcomputer in the BIM mode in a logical bimemory hookup, and gone into a "floating" state waiting for the BICPU microcomputer in the BIM mode to complete the logical bimemory hookup.
PRM mode - Primary Mode - This is one of three different logical modes a BICPU microcomputer can assume. In these three PRM modes, the BICPU microcomputer is logically connected to its "A" bus circuits and the standard memory circuits connected thereto, in exactly the same logical manner as the CPU was connected to its standard memory circuits before being retrofit with the BICPU invention. These three PRM modes logically bridge the gap between microprocessors and the BIM and FLT modes of the BICPU microcomputer.
BIC-BUS - Bimemory Interconnecting Control-BUS - These standard groups of simple, single line, circuits are used to interconnect the "B" or "C" bus circuits of any two different BICPU microcomputers.
ILU - Interrupt Logic Unit - The two new "B" and "C" ILUs monitor and control the BIC-CTRB circuits for the CPU of the BICPU in an asynchronous manner. They enable the CPU of the BICPU invention to go about its data processing tasks, without being interrupted or slowed down, except when the exact BICPU microcomputer needs to be involved in a logical bimemory manner. The ILUs make and complete all logical bimemory hookups, under the control of the CPU of the BICPU microcomputer.
BIC-CTRB - BIC-BUS ConTRol Bus - These circuits comprise the BIC-AD circuits and the "BCR", "BEN" and "BRQ" lines. They are connected to the new buffers and Interconnect Switch on one end and connected to the "B" and "C" bus circuits on the other end. They join and run parallel with the other circuits in the BIC-BUS circuits. They are monitored and controlled by the ILUs, under the control of the CPU of the BICPU microcomputer. Essentially these circuits are new interrupt circuits between two CPUs of two different BICPU microcomputers. These BIC-CTRB circuits are always unique to one set of BIC-BUS circuits. The BIC-CTRB circuits of two different sets of BIC-BUS circuits are never interconnected, and remain unique to just the one set of BIC-BUS circuits they are in. The BICPU microcomputers never directly interconnect the BIC-CTRB circuits. The "B" BIC-CTRB circuits are monitored and controlled by the "B" ILU, and the "C" BIC-CTRB circuits are monitored and controlled by the "C" ILU.
"BCR" line - Bus ControlleR line - This line is set TRUE by the "calling" ILU of a BICPU microcomputer and determines which ILU has control of a set of BIC-CTRB circuits. The "BCR" line is set FALSE by the ILU of the BICPU microcomputer in the BIM mode in a logical bimemory hookup, to initiate logical hang up. The "BCR" line always being set FALSE by the ILU of the BICPU microcomputer in the BIM mode assures that all logical bimemory hookups can be interrupted in a logical manner where the program logic of the bimemory hookup is saved in a logical manner, as desired by the programmer, before the logical bimemory hookup is hung up.
"BEN" line - Bus Enable line - This line enables the logical bimemory hookup to proceed when it is set TRUE by the ILU of the "consenting" BICPU microcomputer. When the "BEN" line is set FALSE by an ILU of a BICPU microcomputer, the logical bimemory hookup is logically hung up, saving the program logic in a logical hang up procedure.
"BRQ" line - Bus ReQuest line - This line is used by the ILUs to generate the "Not Active", "Active BICPU" or "Two or More" signals without requiring external logic circuits outside of the BICPU microcomputers involved in the logical bimemory hookup. This enables simple, single line circuits, without logic, to be used in the BIC-BUS circuits.
BIC-AD lines - Bimemory Interconnecting Control Bus-Address lines - These BIC-AD lines are part of the BIC-CTRB circuits. These BIC-AD lines are not to be confused with the standard address circuits of the CPU of the BICPU microcomputer. These BIC-AD lines are unique to one set of BIC-BUS circuits, and carry the assigned "B" or "C" register number of a BICPU microcomputer being "called" to participate in a logical bimemory hookup. The standard address circuits of the CPU of the BICPU microcomputer can be interconnected between two sets of BIC-BUS circuits by the ILUs of the BICPU microcomputers involved in the logical bimemory hookup. The BIC-AD circuits of two different sets of BIC-BUS circuits are never interconnected. The ILUs monitor these BIC-AD circuits to determine when the address on these circuits match the valid assigned bus number stored in the correct "B" or "C" register, so that the ILUs can determine when they are being "called" by another ILU on this set of BIC-BUS circuits.
DHU - Directed Hang Up - New bimemory instruction causing an ILU to place a special code on the BIC-AD line, subsequently causing both "BEN" lines of each BICPU microcomputer in a given set of BIC-BUS circuits to go FALSE, thereby causing all logical bimemory hookups utilizing all involved BIC-BUS circuits to terminate logically.
NHU - Normal Hang Up - New bimemory instruction causing a normal logical hang up of the various sets of BIC-BUS circuits involved in a logical bimemory hookup. This is used by the programmer to hang up a logical bimemory hookup and return to a PRM mode. It can be compared to the RTN (return) instruction after a subroutine has been completed and the programmer directs the program logic to return to the instruction after the gosubroutine instruction.
GBH - Go Bimemory Hookup - New bimemory instruction causing the BICPU microcomputer to attempt to create a logical bimemory hookup between this BICPU microcomputer and another BICPU microcomputer. This instruction can be compared to a gosubroutine instruction, where the subroutine includes many conditional tests.
